library ieee;
use ieee.std_logic_1164.all;

entity ps2_kb is
  port (
    reset     : in std_logic;
    clock     : in std_logic;

    dev_clk   : in std_logic;
    dev_dat   : in std_logic;

    scode_rdy : out std_logic;

    scode     : out std_logic_vector (7 downto 0);
    error     : out std_logic
  );
end entity ps2_kb;

architecture default of ps2_kb is
  constant PHY_FLT_LEN : positive := 10;
  constant WDT_CTR_LEN : positive := 16;

  signal bit_rdy : std_logic;

  signal scode_rd : std_logic;
  signal clr_rx : std_logic;
  signal rd_bit : std_logic;

  signal timeout : std_logic;
  signal start_wdt : std_logic;
  signal stop_wdt : std_logic;
begin
  ps2_kb_phy_rx_inst : entity work.ps2_kb_phy_rx
    generic map (PHY_FLT_LEN)
    port map (reset, clock, dev_clk, bit_rdy);

  ps2_kb_ctrl_inst : entity work.ps2_kb_ctrl
    port map (reset, clock, dev_dat, bit_rdy, scode_rd, timeout,
      clr_rx, rd_bit, scode_rdy, start_wdt, stop_wdt);

  ps2_kb_wdt_inst : entity work.ps2_kb_wdt
    generic map (WDT_CTR_LEN)
    port map (reset, clock, start_wdt, stop_wdt, timeout);

  ps2_kb_scode_rx_inst : entity work.ps2_kb_scode_rx
    port map (reset, clock, dev_dat, clr_rx, rd_bit, scode, error, scode_rd);
end architecture default;
